1. Field of the Invention
The present invention relates to an asynchronous transfer mode (hereinafter referred to as an ATM) switch of an output buffer type used in asynchronous transfer mode communication systems. More particularly, the present invention relates to an asynchronous transfer mode switch of an output buffer type for performing asynchronous control among a plurality of switching boards. Also, the present invention relates to a method of detecting and correcting error-containing boards in an ATM switch.
2. Description of Related Art
Asynchronous transfer mode switches of an output buffer type used in an ATM communication system increase their processing speed in proportion to switch size. The ATM switches, in most cases, are separately equipped on a plurality of boards and each board mounts a buffer control circuit to control inputting and outputting of data. The ATM switch has a plurality of input ports and output ports and basically functions to switch data input from the input ports and send switched data to the output ports.
Conventional ATM switches have a master board and a plurality of slave boards. In each board, first to Mth first-in first-out buffers (hereinafter, referred to as FIFO buffers) are arranged corresponding to first to Mth output ports. A cell multiplex circuit is arranged in a pre-stage of these FIFO buffers so as to receive input from first to Nth input ports. In addition, in each board, a buffer control circuit for receiving routing control signals is arranged. The buffer control circuit controls the FIFO buffers corresponding to each of the boards.
In the conventional ATM switch, the parallel cell input to the cell multiplex circuit is time-division multiplexed by the cell multiplex circuit. These multiplexed cells are sequentially assigned to the first to the Mth FIFO buffers one by one to be supplied thereto. In this ATM switch, a bit-slice structure is usually used to reduce processing time. In such an ATM switch using the bit-slice structure, the first to the Mth FIFO buffers have bit-slice structure and are formed on a chip of a large scale integrated circuit (LSI) of bit number equal to the value obtained by dividing the bit length of each cell by the number of the boards.
In the conventional ATM switch, since the buffer control circuits of the boards are synchronized with each other, it has been required to detect the time at which any error occurs. Therefore, monitoring cells for monitoring the occurrence of errors from the outside of the boards are input to the ATM switch at regular intervals. Self-testing is executed by, for example the above monitoring cells method. When an error occurs, a reset signal is applied from the master board to the slave board to clear all contents of the FIFO buffers of the board in which the error occurs. Then, operations of the ATM switch are resumed to synchronize the boards with each other.
However, in the conventional ATM switch, a central processing unit CPU supplies the monitoring cells to each of the boards at a prescribed period. When disorders are detected, a re-synchronization process is executed to synchronize these boards. Therefore, a rather long period of time is required to detect disorders of the ATM switch and to cause opening thereof. In addition, when the disorder of the ATM switch is caused during operation, the resetting is carried out to synchronize the buffer control circuits. At that time, all of the boards are reset so that normal ports (highway ports) are reset. Hence, all data stored in the FIFO buffer is cleared. Further, the processing speed of the ATM switch becomes high in proportion to the scale of the ATM switch so that the synchronization control at the time of the re-synchronizing differs greatly.